Few know that the ARC processor architecture is one of the most common architectures, together with ARM, MIPS and x86. Developed in the 1980-ies, the architecture of the ARC is used in different controllers for the widest range of high-tech products, and every year on the basis of the ARC produces about 1.5 billion devices.
The Corporation Synopsys announced a new generation of 32 – bit and 64-bit ARC processor cores, which promise to increase performance compared to predecessors three times, and will also allow you to build systems-on-chip with 12 cores. Thus, the new kernel will allow Synopsys to compete with ARM in several new directions.
“Embedded applications such as controllers for solid-state drives or network equipment is becoming more complex, which requires a significant increase in performance with limited power consumption and form factors,” said John Keter (John Koeter), senior Vice President of marketing and strategy in the field of intellectual property in Synopsys. “With the release of the new architecture ARCv3 and nuclei ARC HS5x and HS6x developers will be able to meet the growing performance requirements of their SoC today and in the future.”
New family of processors, Synopsys DesignWare ARC includes a 32-bit kernel HS56/HS57D/HS58 and 64-bit kernel HS66/HS68. Svezheanonsirovannaya processors designed for a wide range of applications such as controllers for solid-state drives (SSD), network controllers, autopilots for vehicles, infotainment systems for vehicles, and many others. Taking into account the growing demands for volumes of RAM, 64-bit ARC HD6x will allow to create systems with 4.5 Pb of DRAM, while the devices based on ARC HD5x will have to be limited to smaller volumes. However, the actual amount of supported RAM is more likely to be dictated by the operating system in use and visible benefits of 64-bit CPU – the wider conveyor and a large register file.
As for the architectures, DesignWare and DesignWare ARC HS5x ARC HS6x, they support a set of commands ARCv3, which can be expanded instructions APEX (ARC Processor EXtensions), if any clients need something specific. In addition, ARC HS57D is equipped with a digital signal processor ARCv3DSP with the support of 150 teams. New kernel have the depth of the pipeline to 10 stages, can execute two instructions per clock, and equipped with 128-bit module of floating-point operations. At the same time, the most advanced kernel versions support the second level cache (L2) size to 16 MB.
If we talk about performance, the Synopsys says about 3 DMIPS to MHz in integer math, as well as a 5.1 MHz in CoreMark, which is very good for tiny kernels with minimal power consumption. So, 3 DMIPS to MHz is higher than quite a powerful processor Cortex-A55, whereas on a 5.1 CoreMark MHz – faster than any ARM processor for microcontroller.
|Processor cores Synopsys ‘ DesignWare ARC HS5x and HS6x|
|The set of commands||ARCv3|
|Instructions per clock||2|
|Conveyor length||10 steps|
|Precision FPU||FP16, FP32, FP64|
|CPU cluster||12 cores|
|Accelerators per cluster||16 boosters|
|L1||The instruction cache + data Cache|
|L2||–||–||16 MB||–||16 MB|
|The maximum amount of memory||64 GB (depending on OS)||4.5 Petabytes|
|Frequency (t/p 16FFC)||1.8 GHz|
|DMIPS||5400 DMIPS per core / 3 DMIPS to MHz|
|CoreMark||9180 core CoreMark / CoreMark on a 5.1 MHz|
One of the key features of new family of DesignWare ARC HS5x and DesignWare ARC HS6x is the ability to create system-on-chip (system-on-chip, SoC) with 12 CPU cores, General purpose and 16 specialized accelerators. Each core/accelerator in that the processor operates at its own clock frequency and uses its own power system to maximize energy efficiency. Along with the new cores Synopsys also offers on-chip cache-coherent connection to the data transfer rate of 800 GB/s.
This kind of SoC based on the architecture of ARC is not very common today, but taking into account the promising processors auto-pilot, data storage, manage data streams, multicore and various kinds of accelerators will be very useful. The later will allow Synopsys to compete with ARM cores in place in the SoC for the specified applications, which has not happened so far. So, cores, DesignWare ARC HS5x and DesignWare ARC HS6x already interested in the manufacturer of solid state drives Starblaze.
“Developers of high-performance embedded solutions are constantly faced with new challenges in the area of achieving high performance when using large amounts of memory and limitations in the field of energy consumption and size,” said Bruce Chen (Bruce Cheng), chief researcher, Starblaze. “The possibility of a new 32-bit processors ARC HS5x and 64-bit processors HS6x Synopsys in the area of multicore will allow us to move to a new level of energy efficiency, which is not offered by other processors on the market currently”.
Synopsys will offer core ARC HS56, HS57D, HS58, HS66, HS68 and their multiprocessor version HS56MP, HS57DMP, HS58MP, HS66MP, HS68MP, since the third quarter of 2020. In addition, the company will offer a package of ARC MetaWare Development Toolkit for creating circuits on the basis of these nuclei, as well as the simulator and the verifier to verify the SoC before implementation in silicon. As for the support of operating systems, the new kernel will be compatible with a number of Linux distributions, Zephyr, and proprietary OS.